A new asynchronous pipeline is presented for the self-timed design
discipline of quasi-delay insensitivity with dual-rail encoding and
four-phase handshaking. The function blocks of the pipeline consist of
a universal gate (presented in the appendix) which is particularly
simple, comprising only the conventional nand and nor gates, and is
supported by an equally simple development method. The simple quadgate
enables optimisation techniques for completion- detection circuitry
and pipeline architecture. The pipeline is reported to compare
favourably with analogous designs and is demonstrated here on a
selection of 32-bit adders, simulated on 10,000 pairs of random
inputs.