This paper introduces a new method for the synthesis of gate-level
asynchronous controllers. The method is based on a user-level
specification formalism, the path model, and a simple algebraic tool,
the signal calculus, that in combination provide a formalism for the
specification and analysis of path-model designs. The path model view
of communication is state-based as in other asynchronous
finite-state-machine methods; however it focuses on the critical
component of state machines, the paths, and ignores other non-critical
free states. The signal calculus, a temporal lifting of Boolean logic,
helps to formalise path-model specifications algebraically, removing
much of the inadequacy of traditional tabular tools like flow tables,
with their dependency on table cells that is exponential in input
size. The method is demonstrated on two examples.